Machine check architecture provides a mechanism for detecting and reporting hardware (machine) errors. The machine check architecture may employ machine check banks that include one or more error reporting registers for receiving data related to detected machine check errors. A processor may signal the detection of an uncorrected machine check error by generating a machine check exception, which may be reported to an operating system, a virtual machine manager, or other system software. Typical errors reported as machine check exceptions may include: system bus errors; ECC (error correction code) errors; parity errors; cache errors; and TLB (translation lookaside buffer) errors. When a machine check exception is generated, a machine check handler can collect information about the machine check error from the machine check registers. However, when a system has a large number of processors, logical processors, or the like, each having a number of error reporting registers in its view, a machine check handler for each processor or logical processor may have to read a very large number of machine check banks to locate a valid error.